Lightwave Logic and Tower Semiconductor Forge Alliance to Supercharge Global Data Processing
New York, Wednesday, 11 March 2026.
In March 2026, Lightwave Logic and Tower Semiconductor partnered to integrate high-speed modulators into existing chips. This “Zero Change” strategy enables massive 400G data speeds without costly silicon redesigns.
Breaking Down the “Zero Change” Strategy
To understand the significance of the March 11, 2026, announcement, it is crucial to examine the underlying manufacturing process [1]. Tower Semiconductor utilizes its standard 200-millimeter or 300-millimeter complementary metal-oxide-semiconductor (CMOS) production lines to fabricate silicon photonic circuits [2]. During the back-end-of-line (BEOL) stages, Tower etches a specialized “slot” trench into the silicon, which is then filled by spin-coating an organic electro-optic polymer—specifically Lightwave Logic’s Perkinamine—directly over the wafer [2]. During the vital poling stage, Tower maintains processing temperatures below 200 to 250 degrees Celsius (a thermal operating window of 50 degrees) to ensure the polymer’s integrity [2].
Targeting the 400G Horizon and Beyond
The formal integration of Lightwave Logic, Inc. (NASDAQ:LWLG) into Tower’s PH18 process design kit (PDK) is explicitly engineered for next-generation data demands [1]. The collaboration targets bandwidths of 110 gigahertz and beyond, aiming to facilitate 400G per lane applications [1]. These electro-optic polymers are engineered to deliver high-speed data transmission with notably low power consumption, addressing critical energy bottlenecks in modern telecommunications, rapidly expanding data centers, and power-intensive artificial intelligence infrastructure [1].
Scaling Up Production and Foundry Investments
Tower Semiconductor has been methodically building toward this capacity over the past year. By mid-2025, the foundry had already moved into the “Controlled Availability” phase of its Polymer PDK [2]. Earlier, in March 2025, Tower successfully demonstrated 400G per lane capabilities using heterogeneous integration alongside OpenLight, illustrating a viable path toward massive 3.2T data speeds [2]. Following these milestones, Tower Semiconductor CEO Russell Ellwanger confirmed on November 10, 2025, that the company was well underway with customer qualifications [2].